1. Field of Invention
The present invention generally relates to a control chip, and more particularly to a control chip for accelerating memory read-write operations and a method of operating the same.
2. Description of Related Art
Although a control chip is still used to control access to memory data, the speeds of data processing and calculation in current Central Processing Units (CPUs) are accelerating rapidly. Obviously, the performance and efficiency of the whole computer system can be further enhanced if delays caused by the control chip can be effectively minimized.
FIG. 1 shows a schematic diagram illustrative of the connection between the conventional control chip (10) and the CPU (12), wherein the control chip (10) in FIG. 1 encompasses a microprocessor interface (102), a signal conversion circuit (108), and a memory controller (110). A conventional microprocessor interface (102) usually includes a decoder (104) and an AND gate (106), and receives a first address strobe (ADS) signal, a request signal (HREQ[4:0]), and an address bus signal (HA[31:3]) from the CPU (12) by referring to a CPU clock (HCLK). Thereafter, the microprocessor interface (102) performs a decoding operation on the first address strobe (ADS) signal, the request signal (HREQ[4:0]), and the address bus signal (HA[31:3]) via the decoder (104) in the microprocessor interface (102). The decoding results of the first address strobe (ADS) signal, the request signal (HREQ[4:0]), and the address bus signal (HA [31:3]) (determining whether the memory cycle is valid or not will be described later) are fed into the AND gate (106) to determine the state of the second ADS signal. The second ADS signal is a command strobe signal referring to the HCLK that is then directed to the signal conversion circuit (108), which is coupled to the microprocessor interface (102). After the signal conversion circuit (108) receives the second ADS signal, it then converts the second ADS signal referring to the HCLK into a third ADS signal that refers to the memory clocks (DCLK). The third ADS signal is then fed into the memory controller (110), which is coupled to the signal conversion circuit (108), for deriving a memory control signal that refers to the DCLK and meets the memory specifications. The memory control signal is subsequently sent to the memory to control the memory access operations.
Since the CPU reference frequency is different from the memory reference frequency (for example, they are 100 and 133 MHz respectively), the second ADS signal has to be converted via the signal conversion circuit (108) to generate the third ADS signal referring to the DCLK to perform the necessary memory access operations. However, since the signal conversion circuit (108) usually takes a long time to perform the conversion operations, generating the third ADS signal sometimes results in a longer signal delay and affects the following memory access operations.
The request signal (HREQ[4:0]) output from the CPU (12), mentioned above, includes two phases; wherein Phase I is called the “selection phase” and Phase II is called the “length phase”. The selection phase is used to determine the transmission type of the HREQ[4:0] signal, while the length phase is used to indicate the length of the memory being accessed. The address bus signal (HA[31:3] signal) encompasses two phases; wherein Phase I is called the “address phase” and Phase II is called the “byte enable phase”. The address phase is used to specify the address of the memory location, the byte enable phase is used to indicate the data type (including the byte data, word data, double word data or four word data (or, quad word)) that is used for current memory access operations. The conventional memory cycle cannot start until the signal contents in Phases I and II of both the HREQ[4:0] and HA[31:3] signals are manipulated. For example, if an effective memory cycle is to be actuated, it should satisfy the following requirements. Firstly, during Phase I signals, the request selection phase in the HREQ[4:0] signal should be either a memory read signal or a memory write signal, and the address phase in the HA[31:3] signal indicates an effective memory range (i.e. a correct memory access range is indicated). Secondly, a Zero-length (Zlen) signal is not suggested in Phases II of HREQ[4:0] and HA[31:3]. The definition of Zlen signal is illustrated as follows. Firstly, the memory length indicated by the length phase in the HREQ[4:0] signal is “quad word” (therefore, the Phase II of the HREQ[4:0] will contain a “00” signal), and simultaneous all bytes of the byte enable phase in the HA[31:3] signal are disabled (i.e., the byte enable phase consists of continuous 0''s). If the above two conditions are satisfied (i.e., a memory read/write signal, an effective memory address are sent, and Zlen is not suggested), the AND gate (106) will output a logic high signal via the second ADS by reference to the HCLK, therefore a valid memory cycle is actuated to drive the associated memory access operations. Obviously, such a memory access operation cannot begin until the signal contents in Phase II of both the HREQ[4:0] and HA[31:3] signals are analyzed.
FIG. 2 schematically shows a waveform diagram illustrative of a conventional control chip (10) performing a memory access operation, wherein a Pentium 4 CPU having HCLK and DCLK with operating frequencies under 100 and 133 MHz, respectively. Detailed operations of the conventional control chip are described hereinafter according to FIG. 2.
CPU (12) enables a memory cycle when CPU (12) intends to access data from the memory. Whether the memory cycle is valid depends on whether the aforementioned Zlen signal is embedded in Phase II of the HREQ[4:0] and HA[31:3] signals. The microprocessor interface (102) receives a logic low signal via the first ADS signal line when the CPU (12) wants to start a memory cycle, and both the HREQ[4:0] and HA [31:3] that refer to the HCLK are sent by the CPU (12) after a rising edge of the HCLK. Afterwards, the first ADS signal, HREQ[4:0] and HA[31:3] signals are decoded by the decoding circuit (104) in the microprocessor interface (102). The second ADS signal (logic high) that refers to the HCLK is generated via the AND gate (106), as shown in the rising edge (202) of FIG. 2, if the following conditions are met. First, the request selection phase (HREQ_A) in the HREQ[4:0] signal is either a memory read signal or a memory write signal and the address phase (HA_A) in the HA[31:3] signal indicates a valid memory range. Second, the Zlen signal is not recommended in the length phase (HREQ_B) and the byte enable phase (HA_B). That is, the specific condition that the memory length selected by the length phase (HREQ_B) in the HREQ[4:0] signal is “quad word” and simultaneously all bytes of the byte enable phase (HA_B) in the HA[31:3] signal are disabled (i.e. all at logic low or (at 0)) is not suggested. Thereafter, the second ADS signal enables the third ADS signal to be logic high after the rising edge (204) of the DCLK waveform by using the signal conversion circuit (108), wherein the logic high state associated with the third ADS signal is indicated by a rising edge (206), as shown in FIG. 2. The logic high third ADS signal is fed into the memory controller (110) to generate a relative memory control signal that refers to the DCLK and meets the memory specifications, as shown in the rising edge (208), and this control signal is subsequently sent to the memory for activating the associated operation. Notably, the related memory access operation can be processed after the second ADS signal is raised to logic high and maintained for a predetermined period of time. On the other hand, both the HREQ[4:0] and HA[31:3] signals continue in floating states after the first ADS signal is raised from logic low to high, while the current states of the first ADS signal, the HREQ[4:0] and the HA[31:3] signals are frozen until the CPU enables another memory cycle.
Since the control chip (10) does not enable the second ADS signal until an indication that a Zlen signal is detected. The second ADS signal cannot be generated until the Zlen signal has been determined to be absent from Phase II of HREQ[4:0] and HA[31:3]. Moreover, the performance and efficiency of CPU memory data access capabilities are affected by the significant signal delays caused by the signal conversion circuit (108). This implies that when the third ADS signal and the memory control signal appear will be lengthened.